1. Field of the Invention
The present invention relates in general to power consumption of powered devices in integrated circuits and in particular to the active control of such power consumption.
2. Statement of the Problem
The strong demand for low-power computing has been driven by a growing class of portable, battery-operated applications that demand ever-increasing functionalities with low-power consumption. The power consumption is also a limiting factor in integrating more transistors in VLSI (Very Large Scale Integration) chips for portable applications. The resulting heat dissipation also limits the feasible packaging and performance of the VLSI chip and system. Because of the quadratic dependence of power consumption on the supply voltage, reducing the supply voltage level is an effective way to reduce power consumption. However, lower supply voltage for a given technology leads to increased gate delay, and consequently, a powered device has to be operated at a reduced clock rate. More recently, adaptive (or dynamic) voltage scaling (AVS) has been proposed as an effective power management technique. Using this approach, the system supply voltage and the clock frequency of a digital VLSI application are dynamically adjusted to meet the requirements of the powered device. By reducing the supply voltage and the clock frequency of a powered device, adaptive voltage scaling offers, in principle, superior power savings compared to simple on/off power management. Successful applications have included digital signal processing systems, I/O (Input/Output) interface, and general-purpose microprocessors. At a system level, AVS requires a voltage/frequency scheduler that can intelligently vary the speed depending on requirements of a powered device. At the hardware implementation level, a desired AVS component is a controller that automatically generates the minimum voltage required for the desired speed. Desirable features of an AVS controller include: high efficiency of the power converter used to generate the variable supply voltage; an ability to make voltage adjustments over a very wide range of clock frequencies to accommodate processing speeds from stand-by to maximum throughput; and stable and fast transient response to minimize latency and losses when switching between different speed levels. Voltage regulation systems for adaptive voltage scaling include frequency locked loop (FLL) based schemes, phase locked loop (PLL) based schemes, and a delay line based speed detector. In these approaches, the control loop design requires a careful compromise between the loop stability and dynamic response times. In addition, the capture range of PLL or FLL based schemes may limit the achievable range of operating system clock frequencies. Also, since the system clock in a PLL/FLL scheme is generated by a Voltage Controlled Oscillator (VCO) operating from the supply voltage, the system clock suffers from variable clock jitter due to supply voltage noise.
One existing voltage regulation system employs a delay line based clock frequency detector. This system compares the extent of propagation of a signal through two circuits. The first circuit is a replica of a device being powered by the controlled supply voltage, VDD, and the second circuit includes the described replica and one additional component which introduces an additional delay. The result of a comparison of signal propagation in the two circuits generates a value supplied to an accumulator. The accumulator value is appropriately updated with the supplied value, and in turn, supplies the updated accumulator value to a duty cycle controller within a Buck converter. Thereafter, the Buck converter employs a second order system to produce a voltage output based on the updated accumulator value.
The above-described approach involves a third order system which introduces several problems. One problem is that the disclosed delay line requires many system clock cycles to complete an evaluation of the instant clock speed sufficiency. The time needed to update the accumulator and establish a modified duty cycle adds more delay to the system. Finally, the second order circuit located between the duty cycle controller and the voltage output introduces still more delay.
The various processing stages of the existing system risk incurring instability in the control loop which controls the voltage supplied to both the powered device and the delay line circuit. Accordingly, the bandwidth of this voltage regulation system is deliberately limited to provide stability. However, limited regulation bandwidth introduces performance limitations. Specifically, during a high-to-low voltage transition, a slower-than-needed reduction in supply voltage will incur excess power consumption, thereby partially defeating the purpose of voltage control. Moreover, during a low-to-high voltage transition, an excessively slow supply voltage increase runs the risk of disabling proper operation of the powered device.
Separately, it is a problem that twice replicating the circuitry of the powered device in a delay line requires the allocation of much valuable space within an integrated circuit. Therefore, there is a need in the art for a system and method for device voltage regulation which is compact, inherently stable over a wide range of system frequencies, and highly responsive to the instantaneous voltage supply requirements of a powered device.